September 24, 2003, 5:04 PM — The 40-nanometer gap that semiconductor manufacturers are preparing to leap is only as wide as a sliver of a human hair. Years of research and millions of dollars have been spent on equipment and techniques that will enable companies to pack even more transistors onto a silicon chip, or reduce the size of powerful processors.
As the year winds down, Intel Corp., IBM Corp., Texas Instruments Inc. and others are preparing to release their first chips built on a 90 nanometer process technology. The companies are taking slightly different approaches to building these chips, but the results should delight customers looking for more performance and lower power consumption.
Today, most companies are making 0.13-micron chips using CMOS (complementary metal-oxide semiconductor) technology. The shift to 0.09 microns, or 90 nanometers as it is commonly called, will enable chip designers to shrink the widths of the individual wires and the transistor gates on the chip, said Kevin Krewell, senior editor of the Microprocessor Report in San Jose, California.
The 90-nanometer designation refers to the width of the smallest circuit lines on the chip. The actual features on 90-nanometer chips can be quite smaller, down to around 45 nanometers for some of the smallest structures on Intel's chips, said Risto Puhakka, vice president of VLSI Research Inc. in Santa Clara, California, in an e-mail interview.
Smaller processor gates are the immediate benefit of a process technology shrink, Krewell said. The narrower a gate is, the faster the gate can be switched from an "on" position to an "off" position, increasing the maximum clock speed of the chip, he said.
Not only can these processor gates more quickly move signals through a chip, but companies can also pack more of them on a silicon die, Krewell said.
But along with smaller gates and thinner wires comes the problem of power leakage. The structures on a chip are so small and so thin that electrons can dissipate through the wires and gate surfaces while the chip is in standby mode, Krewell said. When moving instructions through the processor, the speed of the movement keeps everything on track, but the static electrons can break through the walls of a processor made on smaller process technologies.
Some companies are attempting to solve this leakage problem by employing a technique called silicon on insulator (SOI). During the manufacturing process, a thin layer of oxide is applied to the silicon wafer, which acts as insulating material to keep electrons inside of the chip's structures.
SOI is a basic improvement to make faster chips that consume less power, said Dean McCarron, principal analyst with Mercury Research Inc. in Cave Creek, Arizona.
IBM and Advanced Micro Devices Inc. (AMD) are currently using this technique in their chips, and plan to use it for their 90 nanometer chips. Motorola Inc. has also used SOI in its 0.13-micron chips, and will continue using the technology at 90 nanometers, said Suresh Venkatesan, director of CMOS platform development.
Motorola is currently validating its compliers for 90-nanometer chips, and plans to have sample products available in the fourth quarter with volume production expected next year, Venkatesan said.
IBM is currently sampling 90 nanometer chips using SOI, and plans to ship those chips in the fourth quarter, said Scott Sykes, an IBM spokesman. Chips made on AMD's 90-nanometer process technology are not expected to make an appearance until the middle of 2004, according to the road map posted on AMD's Web site.
Intel is using a technique called strained silicon in its 90 nanometer chips. Strained silicon results when a layer of silicon germanium is placed atop a layer of silicon. The atoms in both substances seek to align themselves, which stretches the silicon and opens up more room for electrons for flow without increasing the speed or power consumed by the processor.
Intel will eventually adopt SOI in its manufacturing process, but is holding back right now for reasons of cost, Puhakka said. Intel chose not to use SOI in this generation because of concerns about the performance benefits it would receive for the cost required to invest in that technology, but hasn't ruled SOI out of future process designs, said Kevin Teixeira, an Intel spokesman.
The new materials in use at the 90 nanometer level will help chip designers reach new performance heights within their power budgets, but is also cause for concern, Puhakka said.
Any time new materials -- such as low-k dielectrics for chip interconnects, SOI, or strained silicon -- are used in the manufacturing process, surprises that were not foreseen during the planning stages can crop up, he said. This happened to a few chip makers when copper interconnects were introduced with the 0.13-micron process technology, he said.
