IBM Corp. and Advanced Micro Devices Inc. (AMD) have jointly developed a new method for implementing strained silicon technology on both positive and negative transistors, the companies said Monday.
The new manufacturing technique, which the companies are calling Dual Stress Liner, will help improve performance on chips from both companies starting early next year, the companies said. IBM and AMD claim they are the first to show simultaneous performance improvements on both positive and negative transistors using conventional materials.
The companies, as expected, provided more details in a paper presented Monday at the International Electron Devices Meeting (IEDM) in San Francisco.
As it has become more difficult for chip companies to improve transistor performance by simply shrinking transistors, they have turned to alternative techniques to keep improving the performance of their products. Strained silicon is a technique in which a lattice pattern of silicon atoms is either stretched or compressed to improve the speed at which electrons flow through the silicon. Positive transistors run faster when they are compressed, and negative transistors run faster when they are stretched.
However, strained silicon also works in reverse to the detriment of the transistors. Compressing the silicon atoms reduces the performance of negative transistors, while stretching the silicon impedes the performance of positive transistors, said Nick Kepler, vice president of logic technology development with AMD.
In order to get optimal performance from each type of transistor, IBM and AMD created the compressive strain on the silicon wafer with a film of silicon nitride and then removed the film from just the negative transistors, said Lisa Su, vice president of technology development and alliances with IBM. The companies then created the tensile, or stretched, strain on the wafer and removed that layer from the positive transistors, allowing both types of strain to exist side-by-side on the companies' chips, she said.
Other companies, such as Intel Corp., have used materials such as silicon germanium to stretch and compress silicon. Intel is using both silicon germanium and silicon nitride to create strained silicon on its 90nm (nanometer) processors.
Silicon germanium is a difficult material to work with and is also expensive, said Nathan Brookwood, principal analyst with Insight 64, in Saratoga, California. Silicon nitride has been used in semiconductor manufacturing for a long time, which means chip companies are familiar with its behavior during the manufacturing process, he said.
The companies believe that by using their strained silicon techniques on both positive and negative transistors they can improve transistor speed by as much as 24 percent, the statement said.
The strained silicon technology will be integrated into AMD's Opteron and Athlon 64 processors and IBM's Power processors in the first half of 2005.
IBM is planning to use the dual stress liner technology on all of its 90nm products starting next year, Su said. AMD will introduce the technology selectively on both 90nm and 130nm products next year and has already done so with the Athlon FX-55 desktop processor that was introduced earlier this year, Kepler said.
In 2003, AMD and IBM signed an agreement to work on techniques for advanced transistor manufacturing. Joint development teams work at the premier manufacturing facilities of each company, in Dresden, Germany, and East Fishkill, New York, respectively. The companies recently extended that agreement to carry through 2008.
