Carriers? crowded house

By Pauline Rigby, Network World |  Networking

Carriers’ facilities are getting more and more crowded with gear. A couple of weeks ago, Applied Micro Circuits announced a new silicon chip that promises to bring relief to carriers that are rapidly running out of space to house equipment.

The new chip, called Orinoco, promises to shrink the size of Sonet/SDH equipment by orders of magnitude. It does the work of more than a dozen of today’s chips -- enabling an end-to-end, copper-to-optics OC-48 (2.5G bit/sec) SONET system to occupy a single circuit board rather than an entire rack of equipment, as is currently the case.

Orinoco also promises to help equipment manufacturers speed up development times because they’ll be able to buy a ready-made chip rather than having to develop their own subsystems.

What does this mean for enterprise customers? Leasing space in a central office or a point of presence is expensive. If carriers can reduce the amount of space that is needed to house this equipment, costs can be reduced for end users. In addition, if development times are speeded up, that may bode well for enterprise end-users, who eventually will reap the benefits of innovations.

Orinoco takes 12 DS-3 (45M bit/sec) or E-3 (34M bit/sec) channels and aggregates them onto a single OC-12 (622M bit/sec) SONET/ SDH channel. This process is called framing.

However, framing circuits only account for about 20%of the real estate on the Orinoco chip. The rest of the space is devoted to so-called mapping circuits that reduce or eliminate timing errors such as jitter and wander - in short, making sure everything stays synchronous. Timing errors are mostly caused by the fact that DS-3s run at a different clock speed from STS-1s -- the basic unit of SONET -- which has a clock speed of 51.84M bit/sec.

"We had many customers using our Nile chip [a DS-3 to OC-12 framer] with external [phase-locked loops] to smooth the DS-3 clock," says Amit Banerjee, a senior marketing manager at AMCC. "These customers were asking us if we could eliminate the need for costly, hard-to-design-with PLLs."

Banerjee won't say how long it took AMCC's engineers to meet that challenge. However, integrating both analog (PLL circuits) and digital (framing) functions on the same chip was a major hurdle, he says. "It's relatively easy to design a chip with one or two PLLs on it -- people do it," he notes. But 12 PLLs, one per DS-3 or E-3, is a different matter, because the software design tools have to handle an incredibly complex and time-consuming simulation. Mixing analog and digital technologies on the same chip is also challenging -- all the more so because design engineers from different disciplines have to work together, Banerjee says.

According to Banerjee, Orinoco has been sampling for several months. One of the customers testing it is Cyras Systems, which is being acquired by Ciena Corp.

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