April 02, 2013, 12:38 PM — Backed by 100 technology companies, the three largest memory makers announced the final specifications for three-dimensional DRAM, which is aimed at increasing performance for networking and high-performance computing markets.
Micron, Samsung and Hynix are leading the efforts backed by the Hybrid Memory Cube Consortium (HMC). The technology, called a Hybrid Memory Cube, will stack multiple volatile memory dies on top of a DRAM controller.
The DRAM is connected to the controller by way of the relatively new silicon VIA (Vertical Interconnect Access) technology, a method of passing an electrical wire vertically through a silicon wafer.
An illustration of a Hybrid Memory Cube connecting over a bus to a CPU.
Mike Black, chief technology strategist for Micron's Hybrid Memory Cube team, said what the developers did was change the basic structure of DRAM.
"We took the logic portion of the DRAM functionality out of it and dropped that into the logic chip that sits at the base of that 3D stack," Black said. "That logic process allows us to take advantage of higher performance transistors ... to not only interact up through the DRAM on top of it, but in a high-performance, efficient manner across a channel to a host processor.
"So that logic layer serves both as the host interface connection as well as the memory controller for the DRAM sitting on top of it," he added.
The DRAM is broken into 16 partitions, each one with two I/O channels back to the controller. Each Hybrid Memory Cube -- there are two prototypes -- has either 128 or 256 memory banks available to the host system.
The first Hybrid Memory Cube specification will deliver 2GB and 4GB capacity versions of the 3D chip providing aggregate bi-directional bandwidth of up to 160GBps compared with DDR3's 11GBps of aggregate bandwidth and DDR4 with 18GB to 20GB of aggregate bandwidth, Black said.
Jim Handy, director of research firm Objective Analysis, said the Hybrid Memory Cube technology solves significant memory issues. Today's DRAM chips are burdened with having to drive circuit board traces, connectors and the I/O pins of numerous other chips to force data down the bus at gigahertz speeds, which consumes a lot of energy.
The HMC reduces this task to make the DRAM drive only tiny TSVs which are connected to much lower loads over shorter distances," he said. A logic chip at the bottom is the only one burdened with driving the circuit board traces and the processor's I/O pins.
"The interface is 15 times as fast as standard DRAMs ... while reducing power by 70%," Handy said "Basically, the beauty of it is that is gets rid of all the issues that were keeping DDR3 and DDR4 from going as fast as they could."