January 29, 2014, 1:58 PM — ARM's emerging challenge to the x86 architecture in the server space just picked up some serious momentum as AMD announced it will start shipping sample 64-bit ARM processors, along with associated development kits, to partners in the upcoming months.
"What we are talking about is the industry's only 64-bit ARM server from a proven server processor company," said Andrew Feldman, AMD corporate vice president and general manager, in a virtual press conference Monday announcing the pending chips.
The company, which announced in September it would be manufacturing 64-bit ARM processors, demonstrated a prototype of its new processor at a summit for the Open Compute Project (OCP) this week in San Jose, California.
"I think it's significant in that AMD has been firmly entrenched in the server market for almost 15 years. They bring a lot of credibility," said Patrick Moorhead, president and principal analyst at Moor Insights and Strategy. There are only three large companies producing processors for servers today -- Intel, AMD and IBM. So AMD "validates" the idea of ARM in servers.
The pending AMD ARM processors, which will be under the AMD Opteron A1100 Series (or "A-series") nameplate, will be manufactured using 28-nanometer fabrication technology.
The company will start sending samples of the new CPUs, code-named "Seattle," to partners in March or April, as well as development kits for the processor, including a motherboard and set of development software. "These will allow you to begin exploring your software on a server-caliber ARM processor," Feldman said.
It is also contributing to OCP a server design that can be used to build A-series systems. It will use OCP's common slot motherboard architecture called "Group Hug."
Based on the ARM Cortex A57 core design, the AMD Opteron A1100 Series processors will come in either four- or eight-core configurations, with 64GB DRAM. They will have up to 4MB of shared L2 and 8MB of shared L3 cache, and configurable dual DDR3 or DDR4 memory channels with error correcting code that can run up to 1,866 MT (million transfers) per second.
The processors will be built on a system-on-a-chip (SoC) design and will feature eight lanes of PCI-Express Generation 3 I/O, eight Serial ATA 3 ports and two 10 Gigabit Ethernet ports. They will also have encryption/decryption and data compression co-processors, and up to four SODIMM, UDIMM or RDIMM memory modules.